The invention relates to voltage reference devices, and more particularly, to a voltage reference circuit with fast enable and fast disable capabilities.
Voltage reference circuits are an important element for any type of devices, including: test equipment, portable electronics, medical devices, communications systems, and others. A voltage reference circuit is used to provide a steady and reliable voltage level to any electronic circuit. Ideally, the voltage level does not alter when a load or current draw from the electronic circuit is altered. In doing this, optimal voltage conditions for the operation of the electronic circuit are reliably maintained under various conditions.
One type of voltage reference circuit used in the related art is the low drop-out (LDO) voltage regulator. FIG. 1 illustrates a schematic diagram of an LDO regulator 100 according to related art methods. The conventional LDO voltage reference circuit 100 includes an operational amplifier 102, which receives an input reference voltage (VREF) at one input terminal, and receives a feedback voltage at the other input terminal. The operational amplifier 102 acts to amplify the difference between the values between the input terminals, outputting this result at its output terminal. The output terminal of the operational amplifier 102 is coupled to an output transistor 104. The output transistor 104 is typically power device used to supply current to the output node 108. The conventional LDO voltage reference circuit 100 also includes a resistor-capacitor network 106. The resistor-capacitor network 106 includes a load capacitor CL, and resistors R1 and R2 connected in parallel, and is provided between output node 108 and ground potential. A feedback voltage is provided to the operational amplifier 102 from node 110 between resistors R1 and R2 of the resistor-capacitor network 106.
The load capacitor (CL) is typically rather large (e.g., at least 1 .mu.F) in order to ensure loop stabilization. The conventional LDO voltage reference circuit 100 also receives an enable signal that is supplied to the operational amplifier 102. When the enable signal is applied, it “enables” the operational amplifier 102 of the LDO reference circuit 100, from which the output of the differential amplifier 102 activates the output transistor 104 to pull the output node 108 towards the power supply voltage (VDD) and produce a known output reference voltage (VOUT).
However, in some situations, a quick enabling of the reference voltage may be required. If a capacitive load is utilized, it may act to draw current from the output node 108 at a rate faster than what is initially supplied by the output transistor 104. A capacitive load may therefore initially “pull down” the desired output voltage while accumulating enough charge to reach a desired steady state. Therefore, if adequate current and voltage is not initially provided, the desired output voltage may also be reduced until a steady-state is reached.
On the other hand, when the enable signal is not applied to disable the operational amplifier 102, the output of the operational amplifier 102 deactivates the output transistor 104. In this situation, the output voltage (VOUT) would ideally immediately drop to ground potential. However, with reference to the conventional LDO voltage reference circuit 100, the resistor-capacitor network 106 is coupled to the output node 108 and thus, the charge stored at the load capacitor (CL) needs to first discharge through the resistors R1 and R2 before the output voltage (VOUT) can be dropped to approach ground potential.
Because of the RC network 106 coupled to node 108, an RC time constant delay is induced that slows the decay of the output voltage (VOUT) while approaching ground potential. Additionally, because of the typically large capacitance of the load capacitor (CL), and the large resistances of the resistors R1 and R2 (e.g., usually 10 k ohms or more), a large RC time constant results to cause a slow response of output voltage (VOUT) decay in the disable situation. Therefore, while large load capacitors are used by conventional voltage reference circuits to ensure loop stabilization, they inadvertently hinder a rapid disabling of conventional voltage reference circuits.
Failure or delay in providing rapid disabling can lead to undesirable effects. For example, suppose a voltage reference circuit is required to provide a precise voltage reference to an electrical system, such as a portable computing device. In this application, when the voltage reference circuit is disabled, it is supposed to immediately remove power to the portable computing device. However, the slow responsiveness of the output voltage (VOUT) when disabling the voltage reference circuit, causes the portable computing device to undesirably consume power during the time it takes for the voltage reference circuit to become fully disabled (i.e., VOUT=0). Accordingly, this leads to poor power management for the electrical system because the portable computing device will continue to draw power from the power source (e.g., a battery) until the voltage reference becomes fully disabled.
Additionally, it is desirable to ensure the LDO regulator 100 possesses a good power supply ripple rejection ratio (PSRR), which is a measure of how well a circuit rejects ripple coming from the input at various frequencies. A high PSRR is generally desirable; however, it makes loop stability more difficult and limits control of the gain-bandwidth product to control PSRR. Altering the PSRR, therefore, may involve moving of the dominant poles in the device transfer function, which in turn affects bandwidth and noise characteristics. As noise characteristics of the LDO regulator 100 tend to increase with higher PSRR, a suitable tradeoff must therefore be established to meet overall design goals of the LDO regulator.
Therefore, there is a need for voltage reference circuits that not only remain stable, but also can rapidly switch to and from enabled states and disabled states, while providing low noise output and a high PSRR.